Design and Implementation of 12-Bit Arithmetic Logic Unit with 8 Operation Codes to Field Programmable Gate Array
DOI:
https://doi.org/10.26418/elkha.v15i2.64041Keywords:
arithmetic logic unit, field programmable gate array, microprocessor, military aircraft, operation codeAbstract
Digital system has been a part of human life since the invention of the computer with a microprocessor as the central brain. At the heart of a processor is an Arithmetic Logic Unit (ALU) that handles arithmetic and logic operations. The need for high-speed computation to handle complex computations demands microprocessors with higher performance. The existing 4-opcode 8-bit ALU cannot handle multiplication operations, so a solution is needed. In this research, while raising the appeal of beginners, a 12-bit ALU with eight operation codes (opcode) was designed and implemented in Xilinx"™s Field Programmable Gate Array using a schematic diagram approach through logic gates. The designed and implemented ALU provides addition, subtraction, multiplication, square, AND, OR, NAND, and XOR operations. The multiplication operation was tested by performing the computation to provided datasets to obtain the distance travelled by ten military aircraft based on their maximum speed and air travel duration to ensure its performance. The computation performance comparison with an 8-bit ALU with four opcodes was also done. The computation was done for air travel between 10 to 60 minutes with a 10-minute difference. It was found that the 12-bit ALU with eight opcodes outperformed its contender with computation differences between 130.815 ns and 1,468.214 ns. This high performance is supported by the multiply operation that does repeated addition at one time. Based on this finding, the 8-opcode 12-bit ALU is more efficient in the context of computation time, with consistent accuracy. Moreover, the computation time required to calculate military aircraft data with different maximum speeds and air travel duration is only 119.501 ns.
References
S. M. Swamynathan and V. Banumathi, “Design and analysis of FPGA based 32 bit ALU using reversible gates,†Proceedings - 2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering, ICEICE 2017, vol. 2017-Decem, no. April 2017, pp. 1–4, 2017.
V. Sharma, K. Nayanam, S. Shukla, and N. Bhatia, “Design of Energy Efficient ALU on FPGA,†International Journal of Advances in Engineering and Management (IJAEM), vol. 2, no. 2, pp. 5–10, 2008.
N. S. Bedir and F. Kaçar, “Design and Simulation of 64 Bit FPGA based Arithmetic Logic Unit,†Electrica, vol. 19, no. 2, pp. 158–165, 2019.
A. K. Panigrahi, S. Patra, M. Agrawal, and S. Satapathy, “Design and Implementation of a high-speed 4bit ALU using BASYS3 FPGA Board,†in 2019 Innovations in Power and Advanced Computing Technologies (i-PACT), 2019, pp. 1–6.
R. Aliabadian, M. Golsorkhtabaramiri, S. R. Heikalabad, and M. K. Sohrabi, “Design of an ultra-high-speed coplanar QCA reversible ALU with a novel coplanar reversible full adder based on MTSG,†The European Physical Journal Plus, vol. 138, no. 5, p. 481, May 2023.
M. Alharbi, G. Edwards, and R. Stocker, “Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit,†Nanomaterials, vol. 13, no. 17, Sep. 2023.
K. V. B. V. Rayudu, D. R. Jahagirdar, and P. S. Rao, “Modern Design and Testing of High-Speed Vedic ALU Controller using Vedic Algorithms,†Journal of The Institution of Engineers (India): Series B, vol. 104, no. 1, pp. 221–230, Feb. 2023.
H. Wang and X. Chen, “Development and Optimization Design of Digital Logic device based on FPGA,†J Phys Conf Ser, vol. 1345, no. 6, 2019.
B. Özkilbaç, “Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform,†Brilliant Engineering, vol. 1, no. 1, pp. 26–32, Dec. 2019.
A. Borodzhieva, I. Stoev, and V. Mutkov, "Application of Active Learning Methods in the Course 'Digital Electronics' in the Topic Digital Comparators Using FPGA Design," SIITME 2019 - 2019 IEEE 25th International Symposium for Design and Technology in Electronic Packaging, Proceedings, no. October 2019, pp. 160–163, 2019.
A. N. Borodzhieva, I. I. Stoev, and V. A. Mutkov, “FPGA implementation of boolean functions using multiplexers,†in 2019 28th International Scientific Conference Electronics, ET 2019 - Proceedings, 2019.
A. Borodzhieva, I. Stoev, and V. Mutkov, “FPGA Implementation of Boolean Functions Using Decoders and Logic Gates,†SIITME 2019 - 2019 IEEE 25th International Symposium for Design and Technology in Electronic Packaging, Proceedings, no. October, pp. 164–167, 2019.
F. Suryawan, “A project-based approach to FPGA-aided teaching of digital systems,†International Conference on Electrical Engineering, Computer Science and Informatics (EECSI), vol. 2017-Decem, no. September, pp. 19–21, 2017.
A. Rani and N. Grover, “An enhanced FPGA based asynchronous microprocessor design using VIVADO and ISIM,†Bulletin of Electrical Engineering and Informatics, vol. 7, no. 2, pp. 199–208, 2018.
D. Dermawan, M. A. M. Putra, C. B. Waluyo, and B. Sudibya, “Rancang Bangun Arithmetic Logic Unit 8 Bit Pada Spartan 2 Field Programmable Gate Array,†Conference SENATIK STT Adisutjipto Yogyakarta, vol. 6, pp. 185–198, 2020.
S. K. Pattnaik, U. Nanda, D. Nayak, S. R. Mohapatra, A. B. Nayak, and A. Mallick, “Design and implementation of different types of full adders in ALU and leakage minimization,†Proceedings - International Conference on Trends in Electronics and Informatics, ICEI 2017, vol. 2018-Janua, pp. 924–927, 2018.
Military Factory - Global Defense Reference, “Militaryfactory.comâ€,2023.https://www.militaryfactory.com/
M. S. Ali, “Cascaded ripple carry adder based SRCSA for efficient FIR filter,†Indonesian Journal of Electrical Engineering and Computer Science, vol. 9, no. 2, pp. 253–256, 2018.
N. S. Bedir and F. Kaçar, “Design and simulation of 64 bit FPGA based arithmetic logic unit,†Electrica, vol. 19, no. 2, pp. 158–165, 2019.
A. N. Borodzhieva, I. I. Stoev, I. D. Tsvetkova, S. L. Zaharieva, and V. A. Mutkov, “Computer-Based Education in the Course ‘Digital Electronics’ Teaching the Topic ‘Adders-Subtractors,’†in 2020 43rd International Convention on Information, Communication and Electronic Technology, MIPRO 2020 - Proceedings, 2020.
A. Borodzhieva, I. Tsvetkova, S. Zaharieva, D. Dimitrov, and V. Mutkov, “Project-based learning approach applied in the course ‘digital electronics’ for studying the topic ‘binary multipliers,’†in ACM International Conference Proceeding Series, 2021.
F. Nasser and I. Hashim, “Power Optimization of Binary Multiplier Based on FPGA,†Engineering and Technology Journal, 2021.
J. L. Imana, “Low-Delay FPGA-Based Implementation of Finite Field Multipliers,†IEEE Transactions on Circuits and Systems II: Express Briefs, 2021.
M. P. Véstias and H. C. Neto, “Decimal multiplication in FPGA with a novel decimal adder/subtractor," Algorithms. 2021.
P. K. Rai, S. Srivastava, and A. Johri, "Design, Layout and Simulation of 8-bit Arithmetic and Logic Circuits Pad frame using C5 Process for deep submicron CMOS," in 2018 International Conference on Advanced Computation and Telecommunication, ICACAT 2018, 2018.
J. R. Shinde and S. J. Shinde, “An optimization design strategy for arithmetic logic unit,†Universal Journal of Electrical and Electronic Engineering, 2019.
N. Yadav and P. Kumari, “Design of ALU using dual-mode logic with optimized power and speed,†IMPACT 2017 - International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 41–45, 2018.
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